พอดีผมกำลังทำโครงงานวิชาออกแบบลอจิกโดยใช้ ICXC9572 เป็นหัวใจหลักในการทำสกอร์บอร์ดแสดงเวลานี้ ซึ่งอุปกรณ์ภายในมีประกอบไปด้วย สวิตซ์กดติดปล่อยดับสำหรับเลื่อนตำแหน่งคะแนน 4 ตัว X X : X X แสดงผลคะแนนไปยัง Segment แล้วก็ สวิตซ์กดติดปล่อยดับอีก 3 ตัว สำหรับควบคุมการเร่งของเวลาและรีเซ็ทเวลา โดยขับออก Segment อีก 1 ตัว รวมกันมี Segment 2 ตัว ประเด็ดคือ ผมจะเอาโค๊ตทั้งสองตัวนี้มา ใส่เข้ากันยังไงดี โค๊ตสกอร์บอร์ดเลื่อนตำแหน่งผมทำได้เรียบร้อยแล้ว ปัญหาคือผมต้องการจะเอาโค๊ต นาฬิกาใส่เข้าไปอีกที่ (โค๊ตนาฬิกามันเขียนขึ้นมาแยกอีกทีนะครับ ) ท่านใดมีความรู้รบกวนที่นะครับ
--สกอร์บอร์ด
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SB is
port(
count_0 : in std_logic;
count_1 : in std_logic;
count_2 : in std_logic;
count_3 : in std_logic;
clk : in std_logic;
com : out std_logic_vector (3 downto 0);
sgm : out std_logic_vector (6 downto 0));
end SB;
architecture Behavioral of SB is
signal d0,d1,d2,d3,dt : integer range 0 to 9;
signal dtemp : integer range 0 to 3;
begin
process (count_0,count_1,count_2,count_3,clk)
begin
if(clk'event and clk = '1')
then
if(dtemp = 3)
then
dtemp<= 0;
else
dtemp <= dtemp +1;
end if;
end if;
end process;
process (count_0)
begin
if (count_0'event and count_0 = '1')
then
if(d0 = 9)
then
d0<=0;
else
d0<= d0+1;
end if;
end if;
end process;
process (count_1)
begin
if (count_1'event and count_1 = '1')
then
if(d1 = 9)
then
d1<=0;
else
d1<= d1+1;
end if;
end if;
end process;
process (count_2)
begin
if (count_2'event and count_2 = '1')
then
if(d2 = 9)
then
d2<=0;
else
d2<= d2+1;
end if;
end if;
end process;
process (count_3)
begin
if (count_3'event and count_3 = '1')
then
if(d3 = 9)
then
d3<=0;
else
d3<= d3+1;
end if;
end if;
end process;
with dtemp select
dt<= d0 when 0,
d1 when 1,
d2 when 2,
d3 when 3,
0 when others;
with dtemp select
com <= "1110" when 0,
"1101" when 1,
"1011" when 2,
"0111" when 3,
"1111" when others;
with dt select
sgm <="1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
end Behavioral;
--เวลา
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity um2a is
port (
clk,clk2hz : in std_logic;
clr_sw,set_h,set_m : in std_logic;
sgm : out std_logic_vector(6 downto 0);
com : out std_logic_vector (4 downto 0)
);
end um2a;
architecture Behavioral of um2a is
signal count : integer range 4 downto 0;
signal dt,d3,d2,d1,d0 : integer range 0 to 10;
signal collon : integer range 0 to 10;
signal s_count : integer range 0 to 120;
signal clk_source : std_logic;
begin
process (clk)
begin
if (clk'event and clk='1')
then
if (count=4)
then count<=0;
else count<=count+1;
end if;
end if;
end process;
with count select
com <= "01111" when 0,
"10111" when 1,
"11011" when 2,
"11101" when 3,
"11110" when 4,
"11111" when others;
process (set_h)
begin
if (set_h='0')
then clk_source<=clk;
else clk_source<=clk2hz;
end if;
end process;
process (s_count)
begin
if(s_count mod 2=0)
then collon<=2;
else collon<=10;
end if;
end process;
process (clk2hz,clr_sw)
begin
if (clr_sw='0')
then
d3<=0;
d2<=0;
d1<=0;
d0<=0;
else
if(clk_source'event and clk_source='1')
then
if( (s_count=120 and set_h='1' and set_m='1')
or (set_m='0')
or (set_h='0')
)
then s_count <= 0;
if (d0=9)
then d0<=0;
if (d1=5)
then d1<=0;
if ((d2=9 and d3<2)
or (d2=3 and d3=2)
)
then d2<=0;
if (d3=2)
then d3<=0;
else d3 <= d3+1;
end if;
else d2 <= d2+1;
end if;
else d1 <= d1+1;
end if;
else d0 <= d0+1;
end if;
else s_count <= s_count+1 ;
end if;
end if;
end if;
end process;
with count select
dt <= d0 when 4,
d1 when 3,
collon when 2,
d2 when 1,
d3 when 0,
0 when others;
with dt select
sgm <= "1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
end Behavioral;
ใครพอมีความรู้เกี่ยวกับภาษา VHDL มั้งครับ #CPLD
--สกอร์บอร์ด
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SB is
port(
count_0 : in std_logic;
count_1 : in std_logic;
count_2 : in std_logic;
count_3 : in std_logic;
clk : in std_logic;
com : out std_logic_vector (3 downto 0);
sgm : out std_logic_vector (6 downto 0));
end SB;
architecture Behavioral of SB is
signal d0,d1,d2,d3,dt : integer range 0 to 9;
signal dtemp : integer range 0 to 3;
begin
process (count_0,count_1,count_2,count_3,clk)
begin
if(clk'event and clk = '1')
then
if(dtemp = 3)
then
dtemp<= 0;
else
dtemp <= dtemp +1;
end if;
end if;
end process;
process (count_0)
begin
if (count_0'event and count_0 = '1')
then
if(d0 = 9)
then
d0<=0;
else
d0<= d0+1;
end if;
end if;
end process;
process (count_1)
begin
if (count_1'event and count_1 = '1')
then
if(d1 = 9)
then
d1<=0;
else
d1<= d1+1;
end if;
end if;
end process;
process (count_2)
begin
if (count_2'event and count_2 = '1')
then
if(d2 = 9)
then
d2<=0;
else
d2<= d2+1;
end if;
end if;
end process;
process (count_3)
begin
if (count_3'event and count_3 = '1')
then
if(d3 = 9)
then
d3<=0;
else
d3<= d3+1;
end if;
end if;
end process;
with dtemp select
dt<= d0 when 0,
d1 when 1,
d2 when 2,
d3 when 3,
0 when others;
with dtemp select
com <= "1110" when 0,
"1101" when 1,
"1011" when 2,
"0111" when 3,
"1111" when others;
with dt select
sgm <="1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
end Behavioral;
--เวลา
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity um2a is
port (
clk,clk2hz : in std_logic;
clr_sw,set_h,set_m : in std_logic;
sgm : out std_logic_vector(6 downto 0);
com : out std_logic_vector (4 downto 0)
);
end um2a;
architecture Behavioral of um2a is
signal count : integer range 4 downto 0;
signal dt,d3,d2,d1,d0 : integer range 0 to 10;
signal collon : integer range 0 to 10;
signal s_count : integer range 0 to 120;
signal clk_source : std_logic;
begin
process (clk)
begin
if (clk'event and clk='1')
then
if (count=4)
then count<=0;
else count<=count+1;
end if;
end if;
end process;
with count select
com <= "01111" when 0,
"10111" when 1,
"11011" when 2,
"11101" when 3,
"11110" when 4,
"11111" when others;
process (set_h)
begin
if (set_h='0')
then clk_source<=clk;
else clk_source<=clk2hz;
end if;
end process;
process (s_count)
begin
if(s_count mod 2=0)
then collon<=2;
else collon<=10;
end if;
end process;
process (clk2hz,clr_sw)
begin
if (clr_sw='0')
then
d3<=0;
d2<=0;
d1<=0;
d0<=0;
else
if(clk_source'event and clk_source='1')
then
if( (s_count=120 and set_h='1' and set_m='1')
or (set_m='0')
or (set_h='0')
)
then s_count <= 0;
if (d0=9)
then d0<=0;
if (d1=5)
then d1<=0;
if ((d2=9 and d3<2)
or (d2=3 and d3=2)
)
then d2<=0;
if (d3=2)
then d3<=0;
else d3 <= d3+1;
end if;
else d2 <= d2+1;
end if;
else d1 <= d1+1;
end if;
else d0 <= d0+1;
end if;
else s_count <= s_count+1 ;
end if;
end if;
end if;
end process;
with count select
dt <= d0 when 4,
d1 when 3,
collon when 2,
d2 when 1,
d3 when 0,
0 when others;
with dt select
sgm <= "1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
end Behavioral;